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INTEGRATED CIRCUITS
DATA SHEET
PCD5041 DECT burst mode controller
Objective specification Supersedes data of October 1992 File under Integrated Circuits, IC17 1996 Oct 31
Philips Semiconductors
Objective specification
DECT burst mode controller
CONTENTS FEATURES 2 3 4 5 6 6.1 6.1.1 6.1.2 6.2 6.3 6.3.1 6.3.2 6.4 6.4.1 6.4.2 6.4.3 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 6.5.9 6.5.10 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.7 7 8 9 10 10.1 10.2 10.3 10.4 11 12 GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Internal bus and data memory Internal Bus Data Memory Clock generation and correction Programmable communication controller and program memory PCC PCC functions Speech interface 12-slot mode Muting Local call RF interface Serial receiver Serial transmitter Seamless handover RF control signals Synthesizer programming RSSI measurement Local call switching Data synchronization Ciphering machine Comparator/data slicer on PCD5041HZ Microcontroller Interface Function of the microcontroller interface Microcontroller interrupts Watchdog Power-down Survey of registers LIMITING VALUES CHARACTERISTICS PACKAGE OUTLINES SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
PCD5041
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Philips Semiconductors
Objective specification
DECT burst mode controller
1 FEATURES 2 GENERAL DESCRIPTION
PCD5041
* On-chip pre-programmed Communication Controller with embedded firmware for implementation of Traffic Bearer Control (TBC), MAC message handling, scanning, and control of the device's other functional units. * Portable Part (PP) modes * TDMA frame (de)multiplexing * Encryption * Scrambling * CRC generation and checking * Beacon transmission control (by P00 packets) * On-chip comparator for receive data slicer function (only available in the LQFP80 package) * Switches up to12 active speech channels from speech interface to 1152 kbit/s. radio interface, and vice versa * Dual channel speech/data capability * Received Signal Strength Indication (RSSI) measurement, with on-chip 6-bits peak/hold detector * Quality control report * Digital Phase Locked Loop (DPLL) * Synchronization (handset to active bearer, base station to cluster of RFPs) * Seamless handover procedure * Fast (hardware) and slow (software) mute function * 1 kbyte extended RAM memory * On-chip crystal oscillator (13.824 MHz) * Programmable microcontroller clock frequency * Programmable interrupts * Watchdog with two programmable time-outs * Low power consumption in standby mode * Low supply voltage (2.7 to 5.5 V) * SACMOS technology. 3 ORDERING INFORMATION TYPE NUMBER PCD5041H PCD5041HZ
The PCD5041 DECT Burst Mode Controller (BMC) is a custom IC that performs the DECT Physical Layer and MAC Layer time-critical functions, for use in DECT handset products which comply with the following standards (and updates): * DECT CI part 2: Physical layer (DE/RES 3001-2) * DECT CI part 3 : Medium Access Control layer (DE/RES 3001-3) * DECT CI part 7: Security features for DECT (DE/RES 3001-7) * DECT CI part 9: Public Access Profile (DE/RES 3001-9). The PCD5041 has interfaces to: * ADPCM CODECs in the handset mode * A radio transceiver; the interface is fully decoded, and includes power-down signals * An external microcontroller. The PCD5041 is designed to be connected to an ADPCM CODEC (Philips' PCD5032, for example) and an 80C51-type microcontroller. Other microcontrollers (e.g. 68000) and CODECs can also be supported.
PACKAGE NAME QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT319-2 SOT315-1
LQFP80 plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
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Philips Semiconductors
Objective specification
DECT burst mode controller
4 BLOCK DIAGRAM
PCD5041
handbook, full pagewidth
PCD5041
DECT BURST MODE CONTROLLER TIMING, CONTROL, CLOCK GENERATION internal bus
to CODEC/ Highway
SPEECH INTERFACE
DATA MEMORY 2 kbyte RAM
3-wire synthesizer interface Rx/Tx data
RF INTERFACE
PROGRAMMABLE COMMUNICATION CONTROLLER (PCC)
8051/68000 interface
MICROCONTROLLER INTERFACE
PCC PROGRAM MEMORY 4 kbyte ROM
MBH705
Fig.1 Block diagram.
5
PINNING (see Figs 2 and 3) PIN SYMBOL QFP64 LQFP80(1) 80, 1, and 3 to 7 9 11 14 to 12 15 16 17 20 21 22 23 24 25 26 TYPE(2) I/O I I I P O P I O P O I I O address/Data bus address latch enable chip select (active LOW) address bus positive supply 1 microcontroller clock; programmable from fCLK/64 to fCLK, where fCLK is the crystal oscillator frequency negative supply 1 crystal oscillator input crystal oscillator output negative supply watchdog timer output; intended to reset the external microcontroller when expired read (active LOW) write (active LOW) ready signal (active LOW), to initiate wait states in the microcontroller (open drain) 4 DESCRIPTION
AD0 to AD7 ALE CS A8 to A10 VDD1 PROC_CLK VSS1 XTAL1 XTAL2 VSS2 RESET_OUT RD WR RDY
1 to 8 9 10 13 to 11 14 15 16 17 18 19 20 21 22 23
1996 Oct 31
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
PIN SYMBOL QFP64 INT CLK100 VSS3 DO FS3 FS1 FS4 FS2 DI DCK CLK3 ANT_SW T_ENABLE T_POWER_RMP RMT_STAT SYNTH_LOCK VSS4 REF_CLK VDD2 S_ENABLE S_CLK S_DATA S_POWER_DWN VCO_BND_SW 1200 HZ T_DATA SET_OFF_IN TEST1 RSSI_AN TEST2 TEST3 R_DATA 24 25 26 27 - 28 - 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 LQFP80(1) 27 29 31 32 33 34 35 36 37 38 39 40 41 43 44 45 46 47 48 49 51 52 53 54 55 56 57 58 60 - 61 63
TYPE(2) O O P O I/O I/O I/O O I O O O O O I I P O P O O O O O O O I I I I I I interrupt (active LOW) 100 Hz frame timer negative supply 3
DESCRIPTION
3-state data output on the speech interface 8 kHz framing signal to ADPCM CODEC 1 output, for simple base + handset, otherwise 8 kHz framing input 8 kHz framing signal to ADPCM CODEC 1 output, for simple base + handset, otherwise 8 kHz framing input 8 kHz framing signal to ADPCM CODEC 1 output, for simple base + handset, otherwise 8 kHz framing input 8 kHz framing signal to ADPCM CODEC 2 in the base station mode data input on the speech interface simple base + handset; 1152 kHz data clock (output), otherwise 2048 kHz data clock (input) signal 3.456 MHz clock (nominal value, used to adjust system timing) selects one of two antennas Transmitter Enable (active LOW) Transmitter Power Ramp control serial 8-bit data can be read in for each slot; REMote radio lock indication from synthesizer negative supply 4 reference frequency for the synthesizer, i.e. the crystal oscillator clock fCLK positive supply 2 synthesizer enable clock signal, to be used with S_DATA serial data to the synthesizer synthesizer power-down control VCO bandswitch control signal control signal for dual synthesizer schemes serial output data to transmitter switches off the crystal oscillator, and prevents all RF signals from becoming active selects various test modes.; normal operation set to 0 analog signal (for basic DECT systems), peak signal strength measured after a lowpass filter selects various test modes; normal operation set to 0 selects various test modes; normal operation set to 0 receive data
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Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
PIN SYMBOL QFP64 R_ENABLE R_POWER_DWN COMP_NE SLICE_CTR COMP_OUT VDD3 VSS5 COMP_INM VREF COMP_INP VDD(RAM) SYNCPORT RESET MEM_SEL EN_WATCHDOG Notes 54 55 - 56 - 57 58 - 59 - 60 61 62 63 64 LQFP80(1) 64 65 66 67 68 69 70 71 72 73 74 76 77 78 79
TYPE(2) O O I O O P P I I I P I/O I I I
DESCRIPTION receiver enable (active LOW) receiver power-down digital input comparator not_enable (active LOW) slice time constant control digital comparator output positive supply 3 negative supply 5 analog comparator input negative reference input for the A/D converter analog input positive power supply for data RAM in the base station the signal is the SYNCPORT BMC master reset signal selects PCC program memory at microcontroller interface enable watchdog input; when HIGH, the watchdog timer of the BMC is enabled
1. Un-referenced pins for the LQFP80 package are not connected. FS3, FS4 and the comparator signals are only available in the LQFP80 package. 2. All signals which are input or I/O, and which can be floating, need to be pulled up to VDD or down to VSS in order to protect the device against cross-currents. Exceptions are VREF and RSSI_AN, which do not have to be protected.
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Objective specification
DECT burst mode controller
PCD5041
55 R_POWER_DWN
64 EN_WATCHDOG
62 MEM_RESET
61 SYNCPORT
56 SLICE_CTR
54 R_ENABLE
60 VDD(RAM)
63 MEM_SEL
53 R_DATA
handbook, full pagewidth
52 TEST3 51 TEST2 50 RSSI_AN 49 TEST1 48 SET_OFF_IN 47 T_DATA 46 1200_Hz 45 VCO_BND_SW 44 S_POWER_DWN 43 S_DATA 42 S_CLK 41 S_ENABLE 40 VDD2 39 REF_CLK 38 VSS4 37 SYNTH_LOCK 36 RMT_STAT 35 T_POWER_RMP 34 T_ENABLE 33 ANT_SW CLK3 32
MBH706
59 VREF
AD0 1 AD1 2 AD2 3 AD3 4 AD4 5 AD5 6 AD6 7 AD7 8 ALE 9 CSN 10 AD10 11 AD9 12 AD8 13 VDD1 14 PROC_CLK 15 VSS1 16 XTAL1 17 XTAL2 18 VSS2 19 RESET_OUT 20 RD 21 WR 22 RDY 23 INT 24 CLK100 25 VSS3 26 DO 27 FS1 28 FS2 29 DI 30 DCK 31
PCD5041H
Fig.2 Pin configuration, PCD5041H (QFP64 package).
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57 VDD3
58 VSS5
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
handbook, full pagewidth
65 R_POWER_DWN
79 EN_WATCHDOG
68 COMP_OUT
76 SYNCPORT
67 SLICE_CTR
71 COMP_INN
64 R_ENABLE
73 COMP_INP
74 VDD(RAM)
66 COMP_NE
78 MEM_SEL
63 R_DATA
77 RESET
62 TEST3
AD1 n.c. AD2 AD3 AD4 AD5 AD6 AD7 ALE
61 TEST2 60 RSSI_AN 59 n.c. 58 TEST1 57 SET_OFF_IN 56 T_DATA 55 1200_Hz 54 VCO_BND_SW 53 S_POWER_DWN 52 S_DATA 51 S_CLK 50 n.c. 49 S_ENABLE 48 VDD2 47 REF_CLK 46 VSS4 45 SYNTH_LOCK 44 RMT_STAT 43 T_POWER_RMP 42 n.c. 41 T_ENABLE ANT_SW 40
MBH707
72 VREF
1 2 3 4 5 6 7 8 9
n.c. 10
PCD5041HZ
CSN 11 AD10 12 AD9 13 AD8 14 VDD1 15 PROC_CLK 16 VSS1 17 n.c. 18 n.c. 19 XTAL1 20 XTAL2 21 VSS2 22 RESET_OUT 23 RD 24 WR 25 RDY 26 INT 27 n.c. 28 CLK100 29 n.c. 30 VSS3 31 DO 32 FS3 33 FS1 34 FS4 35 FS2 36 DI 37 DCK 38 CLK3 39
Fig.3 Pin configuration, PCD5041HZ (LQFP80 package).
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69 VDD3
70 VSS5
80 AD0
75 n.c.
Philips Semiconductors
Objective specification
DECT burst mode controller
6 FUNCTIONAL DESCRIPTION (see Fig.1) 6.2
PCD5041
Clock generation and correction (see Fig.4)
The PCD5041 has dedicated hardware blocks containing logic for time-critical functions requiring bit or byte-time accuracy. Other functions requiring only slot-time accuracy are performed by software in the Programmable Communication Controller (PCC). This approach offers maximum flexibility during prototyping. 6.1 6.1.1 Internal bus and data memory INTERNAL BUS
The device has an on-chip 13.824 MHz crystal oscillator. From this source, a few frequencies are derived for internal and external use. Frequencies generated for external use are: * 13.824 MHz for the synthesizer reference (pin REF_CLK). This output is only provided if the synthesizer power-down control (output on pin S_POWER_DWN) is not selected. * 0.144 to 13.824 MHz for the microcontroller clock (pin PROC_CLK) * 3.456 MHz for the ADPCM CODEC (pin CLK3) * 1200 Hz (pin 1200_HZ) for dual synthesizer switching * 100 Hz (pin CLK100) indicates start of frame. Nominally, the frequency on pin CLK3 is 3.456 MHz. This frequency is obtained by dividing the crystal frequency by 4. Sometimes, the crystal frequency will be divided by 3 or by 5, to synchronize the combination of the ADPCM CODEC and the device to an external source. For the handset application, the PCD5041 can be synchronized to the incoming radio channel, using the `slot synchronization' event of one active channel, so the handset is locked to one base station.
The function of the internal bus is: * To provide access for all functional blocks to the common data memory * To provide access for the microcontroller-interface and the PCC to all other functional blocks. All functional blocks (speech-interface, RF-interface, microcontroller-interface and PCC) can autonomously use the internal bus to communicate with the common data memory. A bus controller is used to handle the bus priority mechanism. When several blocks request access simultaneously, the request with the highest priority is handled first. 6.1.2 DATA MEMORY
A large part of the data memory is used for the bit rate adaptation between the DECT radio interface and the speech interface. The data memory also acts as the main communication interface between the external microprocessor and the PCC. In a handset, the device uses only 1 kbyte of the common data memory. The remaining 1 kbyte can be used by the microcontroller as an extended data memory for the higher layer software. The microcontroller is not aware of the fact that it is sharing the memory with the PCD5041. From the microcontroller's point of view, the PCD5041's microcontroller-interface plus the common data memory behave as a standard RAM device.
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Objective specification
DECT burst mode controller
PCD5041
handbook, full pagewidth
13.824 MHz system clock
2 6.912 MHz system clock 4 (1) 3.456 MHz system clock for ADPCM codec 3 1152 kHz system/bit clock 144 bit counter 480 clock corrections in this level unless disabled PCD5041's mode register
FSx signals (8 kHz)
slot counter
24
100 Hz frame sync
COMPARATOR
slot counter
16
MBH708
'SYNC' event
Fig.4 Internal clocking scheme of the PCD5041.
6.3 6.3.1
Programmable communication controller and program memory PCC
6.4
Speech interface
The speech interface block performs the following functions: * Connection to a 1152 kbit/s interface in a handset and a simple base station in the so called `12 slot mode' * Autonomous storing/fetching of ADPCM speech data in/from the PCD5041's common data memory, using internal addressing logic * Muting of speech data * Local call. 6.4.1 12-SLOT MODE
The PCC is a RISC-type controller and is used to control functions which are slot-time accurate. It is well suited for bit manipulation, and runs at a clock frequency of 6.912 MHz (equivalent to 3.4Mips). After finishing a task, it switches to a power saving state, from which it returns after a pre-programmed time. 6.3.2 PCC FUNCTIONS
The most important functions of the PCC are to: * Perform the appropriate actions on received messages: PMID and FMID checking, RFPI checking, TBC handling * Prepare A-field messages for transmission * Prepare the RF-interface for the coming slot * Perform the procedures for RSSI and set-up scan, maintain scan counters and timers, assemble the RSSI field in the common data memory * Filter events and indicate them to the microcontroller by interrupt.
This is the normal operating mode for the PCD5041. The 12-slot mode is selected if up to 4 ADPCM CODECs are connected to the PCD5041, where the PCD5041 is the master of these CODECs. In a handset, or in a simple base stations which is connected with up to 4 analog lines to the public network, the PCD5041 is master of the CODECs. Each CODEC is connected with a separate framing reference signal (FS1 to FS4) to the PCD5041. In the QFP64 package, 2 framing signals FS1 and FS2 are available, whereas in the LQFP80 package 4 framing signals can be used (FS1 to FS4). When more CODECs 10
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Philips Semiconductors
Objective specification
DECT burst mode controller
are to be connected, the FS5 to FS12 signals have to be generated externally. When using the framing signals FS1 to FS4, no interface logic is required when using the PCD5032 ADPCM CODEC. A speech-slot control table is used to determine where to store/fetch speech data for transmission and reception. The hardware speech-interface is capable of addressing the right speech buffer for the relevant speech slot, and will maintain a counter carrying the offset to the correct stored/fetched address. 6.4.2 MUTING 6.5 RF interface
PCD5041
Most of the functions performed by the RF interface are under control of the PCC. Specifically, the processing of non-speech data and the programming of functions and registers is done via the PCC. 6.5.1 SERIAL TRANSMITTER
The serial receiver processes the data, which comes from the RF section, and which is already filtered by the synchronization part. The data is latched, using the recovered data clock. The serial receiver will collect the complete A-field and B-field and store it in the common data memory. Before the A-field is received, the A-field start address is programmed by the PCC. Upon reception of A-field nibbles, the address is updated by the serial receiver. Meanwhile, the PCC will program the B-field start address. In Fig.6 the data flow in the serial receiver is shown. Note that almost no decoding of messages is required. Only the header of the A-field needs to be decoded to check if a ciphered message is being received or transmitted, which requires the ciphering to be switched on in the A-field also. 6.5.2 SERIAL RECEIVER
Due to various reasons the quality of the incoming speech data may be degraded significantly. By muting the speech data, these disturbances are not audible (or are less audible) to the user. The PCD5041 performs two types of muting: * Fast muting * Slow muting. Fast muting, which is performed by the PCD5041 automatically, is nothing more than a repetition of the previously received frame (80 speech samples) to the ADPCM CODEC. It is issued if no Sync word was detected. Slow muting is issued by the microcontroller, after having detected a degradation of quality. A slow mute is implemented as a continuous `0000' nibble transmission to the ADPCM CODEC, until slow mute is released. 6.4.3 LOCAL CALL
The serial transmitter performs the reverse of the receiver functions. Several blocks used in the receiver are also used in the transmitter. Amongst these are the CRC-generators, the scrambler, and the address registers. Figure 7 shows the serial transmitter structure. By transmitting the X-CRC twice, the Z-field is transmitted. The handling of the address registers is the same for the transmitter. Transmission of the synchronization sequence (S-field) is done using the same method as the A-field and B-field. The S-field is stored in the common data memory and will be fetched by the transmitter, just before transmission. Two additional functions are not shown in Fig.7: * In the handset the data in the serial transmitter may be advanced by a programmable number of bit periods. This is done to compensate for the delay in the RF section
A local call option is implemented, in order to loopback data from one CODEC to another CODEC, and vice versa, see Fig.5.
handbook, halfpage
0
1
0
1
DO
0
1 speech slots
0
1
DI
* The transmitted data can be inverted (using a switch in the PCD5041 mode register), in order to connect the PCD5041 to VCOs requiring negative modulation.
speech buffer pair
MBH710
Fig.5 Local call switching on speech interface.
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DECT burst mode controller
PCD5041
handbook, full pagewidth
DATA MEMORY
DATA MEMORY READ CONTROL nibble-parallel bit-serial DE-CIPHER CIPHER CONTROL other MUX cs MUX Bprotect DE-CIPHER ok
R-CRC
Cs-DEC. ok
UNSCRAMBLE ok
R-CRC
X-CRC
A-MAP
B-MAP
D-MAP
MBH737
D00 D32
Fig.6 Serial receiver structure.
handbook, full pagewidth
DATA MEMORY
DATA MEMORY READ CONTROL nibble-parallel bit-serial CIPHER CIPHER CONTROL other MUX cs MUX Bprotect CIPHER
R-CRC
Cs-DEC.
UNSCRAMBLE
R-CRC
X-CRC
A-MAP
B-MAP
D-MAP
MBH736
D00 D32
Fig.7 Serial transmitter structure.
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DECT burst mode controller
6.5.3 SEAMLESS HANDOVER
PCD5041
To program various types of synthesizers, a 3-byte shift register is present. Three data formats are supported: 8, 16 or 24 bit words can be selected. The transfer of data from a frequency table in the common data memory to the shift register is under control of the PCC. 6.5.6 RSSI MEASUREMENT (see Fig.8)
Seamless handover guarantees that when speech information is switched from one slot to another, no speech samples are lost, added or displaced. Seamless handover is achieved in the RF interface by: * Using a look-up table containing the correct start addresses of the B-fields in the data memory * The RF receive and transmit blocks move data to/from the data memory block in 4-bit nibbles. 6.5.4 RF CONTROL SIGNALS
The timing of the control signals to the RF section is fixed, but such that an RF delay between 1.5 and 7 s can be tolerated. Only the transmitter ramp signal and the synthesizer enable are programmable within certain limits. 6.5.5
SYNTHESIZER PROGRAMMING
The RSSI measurement in the PCD5041 RF-interface block is done in 3 parts: a peak/hold detector, a 6-bit A/D converter, and an RSSI control unit, which controls the peak/hold detector and the A/D converter. Once per slot time, a sample is fetched by the PCC and saved in the appropriate area of the common data memory. If the radio receiver is active in a particular time slot, the RSSI value will automatically be measured in that slot. Adjustment to the RSSI_AN input level can be made with VREF.
To program a synthesizer, a 3-wire serial interface is used. The signals on this interface are: * S_ENABLE (enable) * S_CLK (clock) * S_DATA (data).
handbook, full pagewidth
RF-INTERFACE
VREF
RSSI_AN
PEAK HOLD
RSSI_AN
6-BIT A/D
6
RSSI CTRL (HW)
internal bus
RSSI PROCESSING (SW in PCC)
RSSI value filtered width = 30 s ( =10 to 40 s)
start_AD RSSI_CTR write in memory
MBH711
Fig.8 RSSI measurement path.
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DECT burst mode controller
6.5.7 LOCAL CALL SWITCHING (see Fig.9)
PCD5041
Bit synchronization is done using a Digital PLL (DPLL), with an oversampling factor of 12, i.e. the DPLL is running at 12 times the data rate. The output from the DPLL is a receive clock signal (RxC), which acts as the enable for a 20-bit shift register. Sync word detection is achieved by checking the incoming data pattern with the expected synchronization field pattern, using a correlator. The correlator has a programmable threshold, so it can accept bit errors in the sync field pattern up to the threshold level. Furthermore, the correlator window is programmable. This means that `SlotSync', which indicates the slot synchronization event, can be detected only during a certain period (the time window).
The PCD5041 provides a local call switching function in the base station. It stores incoming speech nibbles in the common data memory, in the area reserved for that particular receive slot. Then, during the transmit phase, it passes the start pointer of the same data memory area to the transmit block. Thus, the speech data is echoed to the other user. To handle quality degradation for local calls, a mute can be performed at the RF side of the speech buffer. 6.5.8 DATA SYNCHRONIZATION (see Fig.10)
The data synchronization is done in 2 phases: * Bit synchronization * Sync word detection.
handbook, full pagewidth
RF slots Rx1 Rx2 Tx1 Tx2
MBH712
speech buffers in data memory
Fig.9 Local call switching on the RF-side.
handbook, full pagewidth
13.824 MHz filtered data in FILTER
R_DATA (1152 kbits/s)
RxC DPLL
EN D
20-BIT SHIFT REGISTER
XOR base/handset to serial receiver logic
Q0 to Q15
Q16 to Q19
threshold correlator window
MBH713
CORRELATOR (E98A)
SYNC CHECK (1010)
SlotSync
DPLL_sync
Fig.10 Schematic of the receiver synchronization part.
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Objective specification
DECT burst mode controller
The `DPLL_sync' indication should only be used, when `SlotSync' is active. It indicates that the last 4 bits of the pre-amble field (the training sequence) are received correctly, and thus indicates that the DPLL was in lock (synchronized) in time. If the `SlotSync' is active, and the `DPLL_sync' is not, then a sliding interferer might have been detected. If `SlotSync' is not detected, effectively no data is received in that slot. This implies a `fast mute' because speech data received in the previous frame is not destroyed. 6.5.9 CIPHERING MACHINE
PCD5041
automatically by the cipher machine. The contents of the memory space where IV and key are found, are the responsibility of the PCC, and the external microprocessor. 6.5.10 COMPARATOR/DATA SLICER ON PCD5041HZ
The description of the cipher machine is subject to confidentiality. The specification of its algorithms are delivered by ETSI under the terms of a Non-Disclosure Agreement. The cipher machine is under control of the TBC, which is implemented in the PCC. The cipher machine generates 2 fields of ciphering bits: * A_cipher (40 bits) for A-field messages (ciphers tail only) * B_cipher (320 bits) for speech in B-field. The transmitted ciphered bits are then: * A_ciphered: = A XOR A_cipher * B_ciphered: = B XOR B_cipher. On reception by the peer end point, deciphering consists of the same operation thanks to the synchronous generation of A_cipher and B_cipher.
The PCD5041HZ contains a comparator/data slicer. The comparator is a stand-alone circuit. No connections other than power supply are made internally. The comparator can be used as a data slicer for the receiver input. The delay requirements listed in Chapter 8 were derived from this application. Another use of the comparator is in a successive approximation A/D converter to indicate battery low-voltage condition, or in a power-on-reset circuit. When the signal COMP_NE is LOW the comparator is enabled. When COMP_NE is HIGH the comparator is disabled, and the circuit consumes no power. If the comparator is used as a data slicer for the receiver input, the R_DATA is connected to COMP_OUT, the COMP_NE is connected to R_ENABLE, both connection are done externally. The pin COMP_INP is connected to the RF mixer. A proper bias voltage (from the slicer time constant control circuit) is connected to COMP_INM. Another use of the comparator is in a successive approximation A/D converter for battery voltage detection. The pins are protected against ESD damaging, with a protection diode to the positive and negative supply rail. The input pin COMP_NE has a pull-up resistor which keeps the comparator in power-down mode by default.
handbook, halfpage
KEY 64 BITS CIPHER MACHINE KEY 64 BITS
A_cipher (40 bits)
handbook, halfpage
COMP_INP COMP_OUT COMP_INM
B_cipher (320 bits)
MBH714
COMP_NE
MBH715
Fig.11 Cipher machine and its sources.
Fig.12 Circuit schematic of the comparator/data slicer.
The cipher machine is time-multiplexed on a slot basis. Initially, the Initialisation Vector (IV) and the key must be loaded into the cipher machine. Transfer of the IV and key from the common data area to the cipher machine is done
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DECT burst mode controller
6.6 6.6.1 Microcontroller Interface FUNCTION OF THE MICROCONTROLLER INTERFACE 6.6.3 WATCHDOG
PCD5041
The microcontroller interface will provide the following services. * Direct interface to processors which have an INTEL-8051 compatible interface * General interface to processors that can handle `wait states' e.g. 68000-family; in this case glue logic is required * Processor clock signal of which the frequency is programmable in order to adjust instantaneously processor performance to processor work load * A programmable interrupt register * A watchdog timer with time-out periods of 1.25 or 82 seconds, depending on the programming. The microcontroller can address the PCD5041 as any other RAM memory connected to the microcontroller bus. By writing the `Interface-Mode Register', the microcontroller can select the interface mode and its own clock frequency. 6.6.2 MICROCONTROLLER INTERRUPTS
The PCD5041 is equipped with a watchdog timer, which generates a reset towards an external device (e.g. a microcontroller) after time-out. Two (fixed) time-out periods can be programmed; 1.25 s and 82 s. The watchdog function can be disabled by using the EN_WATCHDOG input pin. 6.6.4 POWER-DOWN
The PCC may switch off the 6.912 MHz internal clock, to enter a power saving mode. All blocks, running on this clock are then switched off (i.e. RF-interface, cipher block, speech interface, PCC). This is called the power-down state, and is only used in the handset mode. The 13.824 MHz clock is never switched off. The Timing Control, microcontroller interface, and Bus Controller keep running, in order to remain synchronous with a base station, and to keep the wake-up circuitry active. During power-down the external microcontroller has still access to the common data area. 6.7 Survey of registers
The function of microcontroller Interrupts is to make optimal use of the microcontroller's processing power, and to achieve optimal cooperation between time-critical tasks and less time-critical tasks both executed in software. Three registers are available to handle interrupts. These are: * Interrupt Event Register * Interrupt Enable Register * Interrupt Reset Register. These registers are to be regarded together. Corresponding bits in these registers relate to one and the same event. Bits in the Interrupt Event Register are set by the PCC and are to be reset by the external processor by writing `1's in the corresponding bits in the Interrupt Reset Register. The mask in the Interrupt Enable Register enables the interrupt if corresponding events do occur.
For a survey of all addresses occupied refer to Tables 1 and 2. Some of the address locations are used differently for read and write. The addresses 000 to 7DF are occupied by RAM memory, while the upper 32 bytes are assigned to the hardware registers. A part of the RAM memory is allocated for use by the RF block, cipher block, and the speech interface.
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DECT burst mode controller
Table 1 Hardware register addresses WRITE - S-DATA1 S-DATA2 S-DATA3 - B-field-shift B-field-loc. A-field-loc. window-wide-off window-wide-on window-narrow-off window-narrow-on T-power-rmp-on synth-off RF-control-port slot-cnt-off frame-cnt-ref sync-ref-preset bit-counter-preset frame-counter slot-counter sync-control BMC-mode watchdog-1 watchdog-2 - - interrupt-event interrupt-enable interrupt-reset controller mode - - - RMT-STAT RF-STATUS - - - - - - - - - sync-status slot-counter-copy RSSI bit-counter-copy 1 bit-counter-copy 2 frame-counter slot-counter sync-control BMC-mode - - - - interrupt-event interrupt-enable - controller mode READ Table 2 Fixed RAM locations ADDRESS 740 to 747 748 to 74F 750 to 757 758 to 75F 760 to 767 768 to 76F 770 to 777 778 to 77F 780 to 787 788 to 78F 790 to 797 798 to 79F 7A0 to 7A7 7A8 to 7AA 7AB 7AC to 7AF 7B0 to 7BB 7BC to 7BF 7C0 to 7DF
PCD5041
ADDRESS 7E0 7E1 7E2 7E3 7E4 7E5 7E6 7E7 7E8 7E9 7EA 7EB 7EC 7ED 7EE 7EF 7F0 7F1 7F2 7F3 7F4 7F5 7F6 7F7 7F8 7F9 7FA 7FB 7FC 7FD 7FE 7FF
ENTRY cipher key vector #0 cipher key vector #1 cipher key vector #2 cipher key vector #3 cipher key vector #4 cipher key vector #5 cipher key vector #6 cipher key vector #7 cipher key vector #8 cipher key vector #9 cipher key vector #10 cipher key vector #11 cipher init vector not used XZ field buffer S-field buffer cipher-slot-control-table not used speech-slot-control-table
correlator-threshold measure
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7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II IO Ptot PO IDD ISS Tstg Tj 8 supply voltage all input voltages DC input current DC output current total power dissipation power dissipation per output supply current ground current storage temperature range operating junction temperature CHARACTERISTICS SYMBOL General Tamb VDD VDD(ret) IDD IDD(stb) operating ambient temperature supply voltage RAM retention voltage operating supply current standby supply current clock input duty cycle Digital I/O VIL VOL VIH VOH ILI IO(source) IO(sink) IRDYN(sink) fDCK fFS1 LOW level input voltage LOW level output voltage HIGH level input voltage HIGH level output voltage input leakage current output source current output sink current RDYN output sink current DCK input frequency FS1 input frequency VDD = 3.6 V; 0.4 V VO VDD - 0.4 V VDD = 3.6 V; 0.4 V VO VDD - 0.4 V VDD = 3.6 V; VO = 0.4 V VDD = 5.0 V; VO = 0.4 V n = 1 to 32 2.0 2.0 2.0 - - - 5.0 5.0 5.0 6.0 8 0 0 0.7VDD 0.7VDD - - - - note 1 note 2 All inputs LOW except WRN; XTAL1 running at 14 MHz -25 2.7 1.0 - - 45 - - - 6 1 - PARAMETER CONDITIONS MIN. TYP. PARAMETER MIN. -0.5 -0.5 -10 -10 - - -100 -100 -55 -
PCD5041
MAX. +6.5 VDD + 0.5 +10 +10 +500 30 +130 +130 +100 90 V V
UNIT
mA mA mW mW mA mA C C
MAX.
UNIT C V V mA mA %
+70 5.5 VDD 12 3 55
0.3VDD 0.3VDD VDD VDD 1.0 - - - - -
V V V V A mA mA mA mA kHz kHz
n x 64 -
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PCD5041
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - 1.6 500 - - 3.0 50 - - 0.2 1 - - -
MAX.
UNIT
Oscillator (inputs XTAL1 and XTAL2) gm RF Vi(RSSI_AN) Vi(VREF) Zi(VREF) tconv transconductance feedback resistance VDD = 2.7 V VDD = 3.6 V 0.6 - 200 mS mS k
RSSI Peak detector (6-bit linear A-D converter, for RSSI measurement on input RSSI_AN) input level VREF input voltage VREF input impedance conversion time integral non-linearity differential non-linearity Zi(RSSI_AN) IDD(stb)(comp) IDD(idle)(comp) IDD(1MHz) ILI(comp) Ci Rpu Vcm Vos tpd tpd VOL(comp) VOH(comp) tr tf ten input impedance RSSI_AN PCD5041HZ comparator characteristics supply current (standby) supply current (idle) supply current (1 MHz) input leakage current input capacitance pullup resistance input common mode range max. input offset voltage propagation delay delay difference output level LOW output level HIGH output rise time output fall time enable time note 4 VDD = 3.0 V; note 4 VDD = 3.0 V; note 4 note 5 note 5 note 6 note 7 note 8 note 9 note 8 and 9 IO = 2 mA IO = 2 mA CL = 50 pF CL = 50 pF - - - - - - 1.0 - - - - - - - 10 135 350 - 10 200 - 5 100 10 - 15 15 - - - - 1 - - - 200 - 0.4 - - - 8 A A A A pF k mV ns ns V V ns ns s note 3 during power-down high impedance 0 0 1.0 - 18.4 - - - VDD VREF VDD - - 4 1.5 - V V V k s LSB LSB M Vconv(RSSI_AN) voltage conversion range
VDD - 0.5 V
VDD - 0.4 -
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Notes to the characteristics 1. VDD = 3.0 V; fclk =13.824 MHz; no external load; one speech link active (under typical conditions). 2. VDD = 3.0 V; fclk =13.824 MHz; no external load; after reset. 3. Maximum differential non-linearity at supply voltage 5.5 V and VREF = 1 V.
PCD5041
4. Supply current IDD(stb)(comp) flows when COMP_NE is HIGH. Supply current IDD(idle)(comp) flows when the comparator is in active mode (COMP_NE is LOW). It is the DC current of the comparator when it is not switching, and V(COMP_INP) < V(COMP_INM). The active mode supply current IDD(1MHz) includes the output pulse rate of 1 MHz. 5. For input pins COMP_INP, COMP_INM, COMP_NE. 6. For input pin COMP_NE. 7. The minimum input common mode voltage will be measured at DC levels with, COMP_INM at 1 V DC 30 mV. The same goes for the maximum input common mode voltage at (VDD - 0.5V). 8. These values are not tested in production, and are based upon theoretical estimates and laboratory tests. 9. The propagation delay tpd is measured from the time the differential input voltage equals the offset voltage, to the 50% point of the output transition. The initial differential input voltage is 100 mV and the propagation delay is specified for an input overdrive of 30 mV, and a load capacitance of 50 pF. tpd is valid for both the positive and negative going output transition. The maximum value is valid for the total ranges of temperature, supply voltage and common mode input voltage. The worst case operation conditions are at the minimum supply voltage, the lowest operating temperature and the minimum input common mode voltage. The delay difference tpd gives the difference between tpd for the rising output transition and tpd for the falling output transition and is valid for all operating conditions. The test method to check the maximum delay difference is by measuring the RMS voltage of the output signal.
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9 PACKAGE OUTLINES
PCD5041
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT319-1
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
wM pin 1 index bp 64 1 wM D HD ZD B vM B 19 vM A 20
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.3 A1 0.36 0.10 A2 2.87 2.57 A3 0.25 bp 0.50 0.35 c 0.25 0.13 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.43 1.23 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
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PCD5041
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp 80 1 pin 1 index 20 ZD bp D HD wM B vM B vM A L 21 detail X A A2 A1
Q (A 3) Lp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.25 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1.0 Lp 0.7 0.3 Q 0.70 0.58 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 4 0o
o
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-03-24 95-12-19
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10 SOLDERING 10.1 Introduction
PCD5041
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions: * Do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). * Do not consider wave soldering QFP packages QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 10.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 10.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP and QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 10.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for LQFP or QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
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11 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCD5041
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 12 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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DECT burst mode controller
NOTES
PCD5041
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DECT burst mode controller
NOTES
PCD5041
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DECT burst mode controller
NOTES
PCD5041
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
647021/00/01/pp28
Date of release: 1996 Oct 31
Document order number:
9397 750 01291

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